Title: An Area-Efficient Relaxed Half-Stochastic Decoding Architecture for Nonbinary LDPC Codes
Authors: Lee, Xin-Ru
Yang, Chih-Wen
Chen, Chih-Lung
Chang, Hsie-Chia
Lee, Chen-Yi
Department of Electronics Engineering and Institute of Electronics
Keywords: Nonbinary low-density parity-check (LDPC) codes;relaxed half-stochastic (RHS) algorithm;stochastic decoding
Issue Date: 1-Mar-2015
Abstract: This brief presents an area-efficient relaxed halfstochastic nonbinary low-density parity-check (NB-LDPC) decoder. A novel decoding algorithm, namely, cumulative tracking forecast memory with concealing channel values (CTFM-CC) is proposed to reduce algorithm complexity and maintain bit-errorrate performance as well. Furthermore, the hardware complexity of variable node units (VNUs) is reduced through a truncated architecture, which only keeps the most reliable n probability density functions. To deal with the sum-product-algorithm-to-stochastic conversion of VNU, a dynamic random number generation method, which is used for sampling a stochastic symbol, is also proposed. With these features, a (168, 84) regular-(2,4) NB-LDPC code over GF(16) decoder is implemented in a 90-nm process. According to the results of postlayout simulation, this decoder can deliver a throughput of 1.13 Gb/s with a hardware efficiency of 0.90 Mb/s/K-gate at 286 MHz. Compared to related rate-1/2 NB-LDPC decoders, the proposed decoder achieves the highest hardware efficiency with similar error-correcting capability.
URI: http://dx.doi.org/10.1109/TCSII.2014.2368616
ISSN: 1549-7747
DOI: 10.1109/TCSII.2014.2368616
Volume: 62
Begin Page: 301
End Page: 305
Appears in Collections:Articles