標題: Back-gate forward bias method for low-voltage CMOS digital circuits
作者: Chen, MJ
Ho, JS
Huang, TH
Yang, CH
Jou, YN
Wu, T
電子工程學系及電子研究所
電控工程研究所
Department of Electronics Engineering and Institute of Electronics
Institute of Electrical and Control Engineering
公開日期: 1-六月-1996
摘要: The back-gate forward bias method suitable for present standard hulk CMOS processes has been promoted for low-voltage digital circuit application, A CMOS inverter employing the method has experimentally exhibited the ability of electrically adjusting the transition region of the de voltage transfer characteristics. Transient measurement has further shown that the inverter with a back-gate forward bias of 0.4 V can operate at low supply voltages down to 0.6 V without significant loss in switching speed, Guidelines for ensuring proper implementation of tile method in a bulk CMOS process has been set up against latch-up, parasitic bipolar, impact ionization, and stand-by current, Following these guidelines, a cost-effective low-power, low-voltage, high-density mixed-mode CMOS analog/digital integrated circuits chip with both reasonable speed and improved precision has been projected for the first time.
URI: http://dx.doi.org/10.1109/16.502122
http://hdl.handle.net/11536/1245
ISSN: 0018-9383
DOI: 10.1109/16.502122
期刊: IEEE TRANSACTIONS ON ELECTRON DEVICES
Volume: 43
Issue: 6
起始頁: 904
結束頁: 910
顯示於類別:期刊論文


文件中的檔案:

  1. A1996UM67900009.pdf