Title: A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUs
Authors: Lai, Bo-Cheng Charles
Kuo, Hsien-Kai
Jou, Jing-Yang
Department of Electronics Engineering and Institute of Electronics
Keywords: Multithreaded processors;cache memories;shared memory;performance analysis and design aids
Issue Date: 1-Apr-2015
Abstract: The recently proposed GPGPU architecture has added a multi-level hierarchy of shared cache to better exploit the data locality of general purpose applications. The GPGPU design philosophy allocates most of the chip area to processing cores, and thus results in a relatively small cache shared by a large number of cores when compared with conventional multi-core CPUs. Applying a proper thread mapping scheme is crucial for gaining from constructive cache sharing and avoiding resource contention among thousands of threads. However, due to the significant differences on architectures and programming models, the existing thread mapping approaches for multi-core CPUs do not perform as effective on GPGPUs. This paper proposes a formal model to capture both the characteristics of threads as well as the cache sharing behavior of multi-level shared cache. With appropriate proofs, the model forms a solid theoretical foundation beneath the proposed cache hierarchy aware thread mapping methodology for multi-level shared cache GPGPUs. The experiments reveal that the three-staged thread mapping methodology can successfully improve the data reuse on each cache level of GPGPUs and achieve an average of 2.3 x to 4.3 x runtime enhancement when compared with existing approaches.
URI: http://dx.doi.org/10.1109/TC.2014.2308179
ISSN: 0018-9340
DOI: 10.1109/TC.2014.2308179
Volume: 64
Begin Page: 884
End Page: 898
Appears in Collections:Articles