標題: Electrical characteristic fluctuation of 16-nm-gate high-kappa/metal gate bulk FinFET devices in the presence of random interface traps
作者: Hsu, Sheng-Chia
Li, Yiming
傳播研究所
電機資訊學士班
Institute of Communication Studies
Undergraduate Honors Program of Electrical Engineering and Computer Science
關鍵字: Density of interface traps;Random interface traps;Bulk FinFETs;Interface trap fluctuation;Electrical characteristic fluctuation;Statistical device simulation
公開日期: 25-十一月-2014
摘要: In this work, we study the impact of random interface traps (RITs) at the interface of SiOx/Si on the electrical characteristic of 16-nm-gate high-kappa/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices. Under the same threshold voltage, the effects of RIT position and number on the degradation of electrical characteristics are clarified with respect to different levels of RIT density of state (D-it). The variability of the off-state current (I-off) and drain-induced barrier lowering (DIBL) will be severely affected by RITs with high D-it varying from 5 x 10(12) to 5 x 10(13) eV(-1) cm(-2) owing to significant threshold voltage (V-th) fluctuation. The results of this study indicate that if the level of D-it is lower than 1 x 10(12) eV(-1) cm(-2), the normalized variability of the on-state current, I-off, V-th, DIBL, and subthreshold swing is within 5%.
URI: http://dx.doi.org/10.1186/1556-276X-9-633
http://hdl.handle.net/11536/124276
ISSN: 1556-276X
DOI: 10.1186/1556-276X-9-633
期刊: NANOSCALE RESEARCH LETTERS
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