Title: Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
Authors: Cheng, Ya-Chi
Chen, Hung-Bin
Su, Jun-Ji
Shao, Chi-Shen
Wang, Cheng-Ping
Chang, Chun-Yen
Wu, Yung-Chun
Department of Electronics Engineering and Institute of Electronics
Keywords: Junctionless (JL);Thin-film transistor (TFT);Raised source-and-drain (raised S/D);Dual-gate;Reliability
Issue Date: 11-Dec-2014
Abstract: This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (> 1 mu A/mu m). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I-on/I-off current ratio is over 10(8) A/A for L-g = 1 mu m. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V-th in multi-V-th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
URI: http://dx.doi.org/10.1186/1556-276X-9-669
ISSN: 1556-276X
DOI: 10.1186/1556-276X-9-669
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