標題: AC power loss and signal coupling in very large scale integration backend interconnects
作者: Chen, CC
Kao, HL
Liao, CC
Chin, A
McAlister, SP
Chi, CC
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: AC power;interconnect;RF;Si;3D
公開日期: 1-Apr-2006
摘要: Both the coupling and AC power losses in integrated circuit interconnects in the radio-frequency regime have been measured. The AC power loss decreases with decreasing length, decreasing spacing, and increasing inter metal dielectric (IMD) thickness of parallel metal lines. The unwanted signal coupling and cross-talk monotonically decrease with increasing spacing and decreasing length of the parallel metal lines. However, increasing the IMD thickness from 0.7 to 6 mu m improves the low frequency performance but not the maximum operation frequency. Using a high-resistivity Si (HRS) substrate the AC power loss is significantly reduced but is traded off with an increase in coupling loss. The most effective method of reducing both the AC power and coupling losses is the combined use of three dimensional (3D) integration and an HRS, which gives larger than 1-2 orders of magnitude improvement, up to 20 GHz.
URI: http://dx.doi.org/10.1143/JJAP.45.2992
http://hdl.handle.net/11536/12413
ISSN: 0021-4922
DOI: 10.1143/JJAP.45.2992
期刊: JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS
Volume: 45
Issue: 4B
起始頁: 2992
結束頁: 2996
Appears in Collections:Conferences Paper


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