標題: Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
作者: Luo, Shien-Chun
Chang, Kuo-Chiang
Chen, Ming-Pin
Huang, Ching-Ji
Chiu, Yi-Fang
Chen, Po-Hsun
Cheng, Liang-Chia
Liu, Chih-Wei
Chu, Yuan-Hua
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Digital clocking;dynamic voltage scaling (DVS);flip-flop;process variation;subthreshold circuit
公開日期: 1-十二月-2014
摘要: This brief presents an implementation of ultralow-power microcontrollers that use a separate clock network voltage (SCNV) to correct unexpected errors produced by on-chip variations (OCVs). Separating the clock network voltage requires amendments in the standard cell library and physical designs. Here, the experiments used a 65-nm technology that exhibited considerable OCVs, which caused write and retention errors in clocked storage cells and limited the voltage scaling of microcontrollers. Using the SCNV provides an extraordinary operability to correct errors in the low-voltage clocked storage cells. In addition, the area overhead of the proposed implementation is negligible. Applying the SCNV, the measurement results indicate that the microcontrollers can be operated below 0.3 V, over 0.15-V extension in voltage scaling, and achieve the optimal energy consumption at 0.34 V. Separating the clock network voltage has tradeoff issues in system timing and energy consumption based on the measurement results, and this brief discusses proper applications.
URI: http://dx.doi.org/10.1109/TCSII.2014.2356913
http://hdl.handle.net/11536/124114
ISSN: 1549-7747
DOI: 10.1109/TCSII.2014.2356913
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 61
Issue: 12
起始頁: 947
結束頁: 951
顯示於類別:期刊論文


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