標題: Background calibration of integrator leakage in discrete-time delta-sigma modulators
作者: Wu, Su-Hao
Wu, Jieh-Tsorng
電機工程學系
Department of Electrical and Computer Engineering
公開日期: 1-十二月-2014
摘要: This paper presents an integration-leakage calibration technique for the switched-capacitor integrators in a delta-sigma modulator (DSM). Integrators realized with low-gain opamps are lossy. A DSM that uses lossy integrators exhibits a degraded signal-to-quantization-noise ratio. To calibrate an integrator, its integration leakage is detected in the digital domain, and the leakage compensation is applied to the same integrator in the analog domain. The proposed scheme can calibrate all integrators in a discrete-time DSM of any form. It can be proceed in the background without interrupting the normal DSM operation. The design considerations for the proposed calibration scheme are discussed. Design cases of a 1st-order, a 2nd-order, and a 3rd-order DSM are demonstrated and simulated.
URI: http://dx.doi.org/10.1007/s10470-014-0421-y
http://hdl.handle.net/11536/124112
ISSN: 0925-1030
DOI: 10.1007/s10470-014-0421-y
期刊: ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING
Volume: 81
起始頁: 645
結束頁: 655
顯示於類別:期刊論文


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  1. 000345842200011.pdf