標題: A background timing-skew calibration technique for time-interleaved analog-to-digital converters
作者: Wang, CY
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: analog-digital (A/D) conversion;calibration;timing
公開日期: 1-Apr-2006
摘要: This paper presents a background timing-skew calibration technique for time-interleaved analog-to-digital converters (ADCs). The timing skew between any two adjacent analog-digital (AID) channels is detected by counting the number of zero crossings of the ADCs input while randomly alternating their sampling sequence. Digitally controlled delay units are adjusted to minimize the timing skews among the AID channels caused by the mismatches among the clock routes. The calibration behaviors, including converging speed and timing jitter, are theoretically analyzed and verified with simulations. A 6-bit 16-channel ADC is used as an example.
URI: http://dx.doi.org/10.1109/TCSII.2005.861887
http://hdl.handle.net/11536/12403
ISSN: 1057-7130
DOI: 10.1109/TCSII.2005.861887
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 53
Issue: 4
起始頁: 299
結束頁: 303
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