標題: BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs
作者: Wu, Kai-Chiang
Lin, Ing-Chao
Wang, Yao-Te
Yang, Shuen-Shiang
資訊工程學系
Department of Computer Science
關鍵字: BTI effect;power gating;reliability
公開日期: 1-十月-2014
摘要: Power gating is an effective way to reduce leakage power. This technique uses high V-th transistors, called sleep transistors, to turn off the power supply. However, sleep transistors suffer from the bias temperature instability (BTI) effect, resulting in an increased V-th, and reduced reliability. This paper proposes two BTI-aware sleep transistor sizing algorithms to reduce the total width of sleep transistors based on the distributed sleep transistor network structure. The proposed algorithms reduce total width by more than 16.08%. More area can be reduced if the BTI effect on both sleep and cluster transistors is considered.
URI: http://dx.doi.org/10.1109/TCAD.2014.2334331
http://hdl.handle.net/11536/123975
ISSN: 0278-0070
DOI: 10.1109/TCAD.2014.2334331
期刊: IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
Volume: 33
Issue: 10
起始頁: 1591
結束頁: 1595
顯示於類別:期刊論文


文件中的檔案:

  1. 000344529700012.pdf