標題: Fabrication of High-Performance Poly-Si Thin-Film Transistors With Sub-Lithographic Channel Dimensions
作者: Lee, Ko-Hui
Lin, Horng-Chih
Huang, Tiao-Yuan
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Lithography;poly-Si;thin-film transistor (TFT);tri-gate;trimming
公開日期: 1-十一月-2014
摘要: A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled down below sub-lithographic dimension by using a photoresist (PR) trimming technique. Our results show that the reduction in the planar channel width is essential for suppressing the short-channel effects. Finally, devices with channel length of 120 nm and planar channel width of 110 nm are demonstrated with superior electrical characteristics in terms of small subthreshold swing (146 mV/dec) and low drain-induced-barrier-lowing value (100 mV/V).
URI: http://dx.doi.org/10.1109/JDT.2014.2334361
http://hdl.handle.net/11536/123950
ISSN: 1551-319X
DOI: 10.1109/JDT.2014.2334361
期刊: JOURNAL OF DISPLAY TECHNOLOGY
Volume: 10
Issue: 11
起始頁: 966
結束頁: 970
顯示於類別:期刊論文


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  1. 000344484000004.pdf