標題: Clock Tree Synthesis Considering Slew Effect on Supply Voltage Variation
作者: Wang, Chun-Kai
Chang, Yeh-Chi
Chen, Hung-Ming
Chin, Ching-Yu
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: Algorithms;Design;Clock tree optimization;slew;voltage variation;robust design
公開日期: 1-十一月-2014
摘要: This work tackles a problem of clock power minimization within a skew constraint under supply voltage variation. This problem is defined in the ISPD 2010 benchmark. Unlike mesh and cross link that reduce clock skew uncertainty by multiple driving paths, our focus is on controlling skew uncertainty in the structure of the tree. We observe that slow slew amplifies supply voltage variation, which induces larger path delay variation and skew uncertainty. To obtain the optimality, we formulate a symmetric clock tree synthesis as a mathematical programming problem in which the slew effect is considered by an NLDM-like cell delay variation model. A symmetry-to-asymmetry tree transformation is proposed to further reduce wire loading. Experimental results show that the proposed four methods save up to 20% of clock tree capacitance loading. Beyond controlling slew to suppress supply-voltage-variation-induced skew, we also discuss the strategies of clock tree synthesis under variant variation scenarios and the limitations of the ISPD 2010 benchmark.
URI: http://dx.doi.org/10.1145/2651401
http://hdl.handle.net/11536/123925
ISSN: 1084-4309
DOI: 10.1145/2651401
期刊: ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
Volume: 20
顯示於類別:期刊論文


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  1. 000345523400003.pdf