標題: Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
作者: Ker, MD
Chen, SL
Tsai, CS
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: body effect;charge pump circuit;gate-oxide reliability;high-voltage generator;low voltage
公開日期: 1-May-2006
摘要: A new charge pump circuit with consideration of gateoxide reliability is designed with two pumping branches in this paper. The charge transfer switches in the new proposed circuit can be completely turned on and turned off, so its pumping efficiency is higher than that of the traditional designs. Moreover, the maximum gate-source and gate-drain voltages of all devices in the proposed charge pump circuit do not exceed the normal operating power supply voltage (VDD). Two test chips have been implemented in a 0.35-mu m 3.3-V CMOS process to verify the new proposed charge pump circuit. The measured output voltage of the new proposed four-stage charge pump circuit with each pumping capacitor of 2 pF to drive the capacitive output load is around 8.8 V under 3.3-V power supply (VDD = 3.3 V), which is limited by the junction breakdown voltage of the parasitic pn-junction in the given process. The new proposed circuit is suitable for applications in low-voltage CMOS processes because of its high pumping efficiency and no overstress across the gate oxide of devices.
URI: http://dx.doi.org/10.1109/JSSC.2006.872704
http://hdl.handle.net/11536/12293
ISSN: 0018-9200
DOI: 10.1109/JSSC.2006.872704
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 41
Issue: 5
起始頁: 1100
結束頁: 1107
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