標題: Effective electrostatic discharge protection circuit design using novel fully silicided N-MOSFETs in sub-100-nm device era.
作者: Lee, JW
Li, YM
電信工程研究所
友訊交大聯合研發中心
Institute of Communications Engineering
D Link NCTU Joint Res Ctr
關鍵字: circuit design;design;electrostatic discharge (ESD);fabrication;floating charge effect;fully silicided;measurement;nanodevice;semiconductor devices;silicide-blocked;simulation;ULSI
公開日期: 1-五月-2006
摘要: In this paper, the floating charge effect is considered in the design of new fully silicided NMOSFETs for designing electrostatic discharge (ESD) protection circuit consisting of nanodevices. According to the designed, fabricated, and studied new fully silicided ESD protection nanodevices (e.g., 90-nm CMOS devices), our investigation demonstrates that there is a significant improvement in sustaining ESD robustness than that of the conventional fully silicided device. Furthermore, it has an excellent electrical efficiency compared with that of drain-ballast resistor-tied devices. Moreover, our novel design exhibits a higher driving current and better reliability without suffering the off-state current of the fully silicided devices. Those good characteristics are especially suitable for the output buffer design in which both driving capability and ESD robustness have to be considered.
URI: http://dx.doi.org/10.1109/TNANO.2006.874044
http://hdl.handle.net/11536/12278
ISSN: 1536-125X
DOI: 10.1109/TNANO.2006.874044
期刊: IEEE TRANSACTIONS ON NANOTECHNOLOGY
Volume: 5
Issue: 3
起始頁: 211
結束頁: 215
顯示於類別:會議論文


文件中的檔案:

  1. 000237822400012.pdf