標題: Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation
作者: Chou, JM
Hsieh, YT
Wu, JT
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: averaging;clocks;delay-locked loops (DLLs);interpolation;phase-locked loops (PLLs)
公開日期: 1-May-2006
摘要: Circuit techniques using resistor strings (R-strings) and resistor rings (R-rings) for phase averaging and interpolation are described. Phase averaging can reduce phase errors, and phase interpolation can increase the number of available phases. In addition to the waveform shape, the averaging and the interpolation performances of the R-strings and R-rings are determined by the clock frequency normalized by a RC time constant of the circuits. To attain better phase accuracy, a smaller RC time constant is required, but at the expense of larger power dissipation. To demonstrate the resistor ring's capability of phase averaging and interpolation, a 125-MHz 8-bit digital-to-phase converter (DPC) was designed and fabricated using a standard 0.35-mu m SPQM CMOS technology. Measurement results show that the DPC attains 8-bit resolution using the proposed phase averaging and interpolation technique.
URI: http://dx.doi.org/10.1109/TCSI.2006.869905
http://hdl.handle.net/11536/12273
ISSN: 1057-7122
DOI: 10.1109/TCSI.2006.869905
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 53
Issue: 5
起始頁: 984
結束頁: 991
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