標題: A novel design of high-speed divide-by-3/4 counter for a dual-modulus prescaler
作者: Shih, Yi-Shing
Tarng, Jenn-Hwan
電信工程研究所
Institute of Communications Engineering
關鍵字: prescaler;high-speed circuits;synchronous counter
公開日期: 25-六月-2006
摘要: A novel design for a high-speed divide-by-3/4 counter is presented. The proposed design reduces not only the critical path delay but also the feedback path delay, hence it can increase the operating speed. With this divide-by-3/4 counter, a divide-by-127/128 dual-modulus prescaler (DMP), implemented in 0.18 mu m CMOS technology, shows a maximum operating frequency of 7.0 GHz with 2.4mW power consumption at 1.8V supply voltage, which has 25% speed improvement and still consumes less power as well compared to the recently-reported one.
URI: http://dx.doi.org/10.1587/elex.3.276
http://hdl.handle.net/11536/12133
ISSN: 1349-2543
DOI: 10.1587/elex.3.276
期刊: IEICE ELECTRONICS EXPRESS
Volume: 3
Issue: 12
起始頁: 276
結束頁: 280
顯示於類別:期刊論文


文件中的檔案:

  1. 000241914100004.pdf