標題: Spatially resolving the hot carrier degradations of poly-Si thin-film transistors using a novel test structure
作者: Lin, HC
Lee, MH
Chang, KH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: grain boundary;hot-carrier (HC) effects;poly-Si;test structure;thin-film transistor (TFT)
公開日期: 1-七月-2006
摘要: A novel thin-film transistor test structure is proposed for monitoring the device hot-carrier (HQ degradations. The new test structure consists of several source/drain electrode pairs arranged in the direction perpendicular to the normal (i.e., lateral) channel of the test transistor. This unique feature allows, for the first time, the study of spatial resolution of HC degradations along the channel of the test transistor after stressing. The extent of degradation as well as the major degradation mechanisms along the channel of the test transistor can be clearly identified.
URI: http://dx.doi.org/10.1109/LED.2006.876314
http://hdl.handle.net/11536/12113
ISSN: 0741-3106
DOI: 10.1109/LED.2006.876314
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 27
Issue: 7
起始頁: 561
結束頁: 563
顯示於類別:期刊論文


文件中的檔案:

  1. 000238712200011.pdf