標題: Employing pipelined thinning architecture for real-tire fingerprint verifier
作者: Hsiao, P. Y.
Chen, X. Z.
Lin, C. C.
Hua, C. H.
Chang, C. C.
資訊工程學系
Department of Computer Science
公開日期: 1-Sep-2006
摘要: Thinning is a very important operation in the pre-processing stage of fingerprint recognition. With the availability of fast thinning hardware, real-time image processing applications can be achieved. The authors introduce a detailed hardware architecture design of a thinning processor used in an embedded fingerprint recognition system. The proposed thinning algorithm has a parallel-pipelining structure suited to hardware realisation, which is implemented and verified using FPGA. Equipped with a modification unit array, a designated operating schedule, and an address generator based on systolic counter, this thinning processor is able to perform a thinning operation within 0.07 s at 40 MHz for a 512 x 512 picture, which is at least 40 times faster than software execution. Consequently, the proposed thinning processor was successfully integrated into a real-time fingerprint recognition system.
URI: http://dx.doi.org/10.1049/ip-cdt:20050200
http://hdl.handle.net/11536/11869
ISSN: 1350-2387
DOI: 10.1049/ip-cdt:20050200
期刊: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Volume: 153
Issue: 5
起始頁: 348
結束頁: 354
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