標題: Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors
作者: Ker, Ming-Dou
Chen, Shih-Lun
Tsai, Chia-Sheng
電機學院
College of Electrical and Computer Engineering
關鍵字: gate-oxide reliability;gate-tracking circuit;interface;mixed-voltage I/O buffer
公開日期: 1-Sep-2006
摘要: Overview on the prior designs of the mixed-voltage I/O buffers is provided in this work. A new 2.5/5-V mixed-voltage I/O buffer realized with only thin gate-oxide devices is proposed. The new proposed mixed-voltage I/O buffer with simpler dynamic n-well bias circuit and gate-tracking circuit can prevent the undesired leakage current paths and the gate-oxide -reliability problem, which occur in the conventional CMOS I/O buffer. The new mixed-voltage I/O buffer has been fabricated and verified in a 0.25-mu m CMOS process to serve 2.5/5-V I/O interface. Besides, another 2.5/5-V mixed-voltage I/O buffer without the subthreshold leakage problem for high-speed applications is also presented in this work. The speed, power consumption, area, and-noise among these mixed-voltage I/O buffers are also compared and discussed. The new proposed mixed-voltage I/O buffers can be easily scaled toward 0.18- mu m (or below) CMOS processes to serve other mixed-voltage I/O interfaces, such as 1.8/3.3-V interface.
URI: http://dx.doi.org/10.1109/TCSI.2006.882816
http://hdl.handle.net/11536/11816
ISSN: 1057-7122
DOI: 10.1109/TCSI.2006.882816
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 53
Issue: 9
起始頁: 1934
結束頁: 1945
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