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dc.contributor.authorTseng, Sheng-Cheen_US
dc.contributor.authorMeng, Chinchunen_US
dc.contributor.authorLi, Shao-Yuen_US
dc.contributor.authorSu, Jen-Yien_US
dc.contributor.authorHuang, Guo-Weien_US
dc.date.accessioned2014-12-08T15:15:43Z-
dc.date.available2014-12-08T15:15:43Z-
dc.date.issued2006-10-01en_US
dc.identifier.issn0895-2477en_US
dc.identifier.urihttp://dx.doi.org/10.1002/mop.21876en_US
dc.identifier.urihttp://hdl.handle.net/11536/11746-
dc.description.abstractThis paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in the standard 0.35-mu m 2P4M CMOS technology. This frequency divider is composed of a synchronous current mode logic divide-by-4/5 prescaler, an asynchronous true single-phase-clock toggle flip-flops divide-by-64 divider, and a digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 to 2.9 GHz. Most of the input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2 X 0.7 mm(2). (C) 2006 Wiley Periodicals, Inc.en_US
dc.language.isoen_USen_US
dc.subjectprescaleren_US
dc.subjectCMOSen_US
dc.subjectsingle-endeden_US
dc.subjectcurrent mode logicen_US
dc.subjectdivide-by-4/5en_US
dc.titleSingle-ended frequency divider with moduli of 256-271en_US
dc.typeArticleen_US
dc.identifier.doi10.1002/mop.21876en_US
dc.identifier.journalMICROWAVE AND OPTICAL TECHNOLOGY LETTERSen_US
dc.citation.volume48en_US
dc.citation.issue10en_US
dc.citation.spage2096en_US
dc.citation.epage2100en_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.identifier.wosnumberWOS:000239682100057-
dc.citation.woscount0-
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