標題: Single-ended frequency divider with moduli of 256-271
作者: Tseng, Sheng-Che
Meng, Chinchun
Li, Shao-Yu
Su, Jen-Yi
Huang, Guo-Wei
電信工程研究所
Institute of Communications Engineering
關鍵字: prescaler;CMOS;single-ended;current mode logic;divide-by-4/5
公開日期: 1-十月-2006
摘要: This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in the standard 0.35-mu m 2P4M CMOS technology. This frequency divider is composed of a synchronous current mode logic divide-by-4/5 prescaler, an asynchronous true single-phase-clock toggle flip-flops divide-by-64 divider, and a digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 to 2.9 GHz. Most of the input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2 X 0.7 mm(2). (C) 2006 Wiley Periodicals, Inc.
URI: http://dx.doi.org/10.1002/mop.21876
http://hdl.handle.net/11536/11746
ISSN: 0895-2477
DOI: 10.1002/mop.21876
期刊: MICROWAVE AND OPTICAL TECHNOLOGY LETTERS
Volume: 48
Issue: 10
起始頁: 2096
結束頁: 2100
顯示於類別:期刊論文


文件中的檔案:

  1. 000239682100057.pdf