標題: Single-chip FPGA implementation of a digital VRM controller with interlaced sampling and control technique
作者: Lin, Yu-Tzung
Wang, Yi-Chung
Tzou, Ying-Yu
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: digital VRM controller;single-chip FPGA implementation;interlaced sampling and control scheme;synchronous current sampling technique
公開日期: 2007
摘要: This paper presents the design and implementation of a singe-chip FPGA based digital VRM controller for multi-phase synchronous buck converters with interlaced current sampling and load current feed-forward compensation techniques. The sampling of the inductor current is synchronized with the middles of leading and trailing edges of the PWM signal of each synchronous buck converter for both turn-on and turn-off. The proposed sampling scheme has a high noise immunity to the common-mode switching noises induced by the switching of the MOSFET and its parasitic junction capacitances resulted by the heat sink. A true average current signal with minimum response time can be measured with accuracy within a switching period. The timing clocks for the digital controller and the digital PWM generator are interlaced with each other to achieve a minimum delay at a same sampling and switching frequency. A digital interface is designed for the connected microprocessor load to adjust the output voltage and provide feed-forward load current compensation according to its clock rate, loading factor, and pipeline scheduling. The realization scheme for the proposed digital VRM controller has been described. Simulation analysis and experimental verifications are given to illustrate the fast dynamic response control of VRM for advanced microprocessors.
URI: http://hdl.handle.net/11536/11734
http://dx.doi.org/10.1109/PESC.2007.4342206
ISBN: 978-1-4244-0654-8
ISSN: 0275-9306
DOI: 10.1109/PESC.2007.4342206
期刊: 2007 IEEE POWER ELECTRONICS SPECIALISTS CONFERENCE, VOLS 1-6
起始頁: 1441
結束頁: 1447
Appears in Collections:Conferences Paper


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