標題: Design of mixed-voltage I/O buffer by using NMOS-blocking technique
作者: Ker, Ming-Dou
Chen, Shih-Lun
電機學院
College of Electrical and Computer Engineering
關鍵字: gate-oxide reliability;hot-carrier degradation;interface;junction breakdown;mixed-voltage I/O buffer
公開日期: 1-十月-2006
摘要: An nMOS-blocking technique for mixed-voltage I/O buffer realized with only 1 x V-DD devices can receive 2 x V-DD, 3 x V-DD, and even 4 x V-DD input signal without the gate-oxide reliability issue is proposed. In this paper, the 2 x V-DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.25-mu m 2.5-V CMOS process to serve 2.5/5-V mixed-voltage interface. The 3 x V-DD input tolerant mixed-voltage I/O buffer by using the nMOS-blocking technique has been verified in a 0.13-mu m 1-V CMOS process to serve 1/3-V mixed-voltage interface. The proposed nMOS-blocking technique can be extended to design the 4 x V-DD, 5 x V-DD, and even 6 x V-DD input tolerant mixed-voltage I/O buffers. The limitation of the nMOS-blocking technique is the breakdown voltage of the pn-junction in the given CMOS process.
URI: http://dx.doi.org/10.1109/JSSC.2006.881546
http://hdl.handle.net/11536/11710
ISSN: 0018-9200
DOI: 10.1109/JSSC.2006.881546
期刊: IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume: 41
Issue: 10
起始頁: 2324
結束頁: 2333
顯示於類別:期刊論文


文件中的檔案:

  1. 000240697600016.pdf