標題: Study on electrical degradation of p-type low-temperature polycrystalline silicon thin film transistors with C-V measurement analysis
作者: Huang, Shih-Che
Kao, Yu-Han
Tai, Ya-Hsiang
光電工程學系
顯示科技研究所
Department of Photonics
Institute of Display
關鍵字: thin film transistor;poly-Si;LTPS;p-type;C-V (capacitance-voltage) measurement
公開日期: 25-Nov-2006
摘要: Laser recrystallized low-temperature poly-silicon (LTPS) films have attracted attention for their application in thin-film transistors (TFTs), which are widely used in active matrix display. However, the degradation behavior of p-type LTPS TFTs is not quite clarified yet. In this paper, the instability mechanisms of p-channel LTPS TFTs under DC bias stress have been investigated. From the IV transfer curves, it was observed that LTPS TFT's mobility increases after stress at some bias conditions. This degradation is most likely caused by interface traps between the poly-Si thin film and the gate insulator, as well as the damaged junction of the drain from stress. In this work, the assumption is examined via C-V measurement. It is found that the C-GD curves of the stressed TFT slightly increase for the gate voltage smaller than the flat band voltage V-FB. However, the C-Gs curves of the stressed device are almost the same as those before stress. By employing simulation, it is found that the degradation of p-type TFTs under this stress condition is mainly caused by the trapped charges at the interface between the gate and the drain region, which is generated by the high voltage difference applied during DC bias stress. (c) 2006 Elsevier B.V. All rights reserved.
URI: http://dx.doi.org/10.1016/j.tsf.2006.07.127
http://hdl.handle.net/11536/11522
ISSN: 0040-6090
DOI: 10.1016/j.tsf.2006.07.127
期刊: THIN SOLID FILMS
Volume: 515
Issue: 3
起始頁: 1206
結束頁: 1209
Appears in Collections:Conferences Paper


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