Title: Direct digital frequency synthesis based on a two-level table-lookup scheme
Authors: Chen, Sau-Gee
Chih, Jen-Chuan
Chou, Jun-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Keywords: direct digital frequency synthesizer;DDFS algorithm;two-level table lookup scheme
Issue Date: 1-Dec-2006
Abstract: In this work, a new direct digital frequency synthesizer (DDFS) is proposed, which is based on a new two-level table-lookup (TLTL) scheme combined with Taylor's expansion. This method only needs a lookup-table size of total n x 2(n/4+1) + (n/4 - 2) x 2(n/4) bits, one (n + 1) x 3n/4-bit multiplier, one n x 3n/4-bit multiplier and two additional smaller multipliers, to generate both sine and cosine values (where n is the output precision). Compared with several notable DDFS's, the new design has a smaller lookup-table size and higher SFDR (Spurious Free Dynamic Range) for high-precision output cases, at comparable multiplier and adder complexities. The DDFS is verified by FPGA and EDA tools using Synopsys Design Analyzer and UMC 0.25 mu m cell library, assuming 16-bit output precision. The designed 16-bit DDFS has a small gate count of 2,797, and a high SFDR of 110 dBc.
URI: http://dx.doi.org/10.1007/s11265-006-9763-8
http://hdl.handle.net/11536/11472
ISSN: 0922-5773
DOI: 10.1007/s11265-006-9763-8
Journal: JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY
Volume: 45
Issue: 3
Begin Page: 153
End Page: 160
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