標題: Design of memory sub-system with constant-rate bumping process for H.264/AVC decoder
作者: Li, Chih-Hung
Peng, Wen-Hsiao
Chiang, Tihao
資訊工程學系
電子工程學系及電子研究所
Department of Computer Science
Department of Electronics Engineering and Institute of Electronics
關鍵字: H.264/AVC;DRAM controller;bumping process;transaction level modeling
公開日期: 1-Feb-2007
摘要: In this paper, we propose an efficient memory sub-system and a constant-rate bumping process for a H.264/AVC decoder conforming to High profile@ Level 4. To efficiently utilize the throughput of external DRAM a synchronization buffer is employed as a bridge for reformatting the read/write data exchanged between the on-chip hardware and the off-chip DRAM In addition, we optimize the issues of read/write commands and adaptively enable the auto-precharge function by monitoring the motion information of a submacroblock. Furthermore, a regulation buffer with size comparable to the decoded picture buffer is created to ensure a constant output rate of decoded pictures for any conformed prediction structures. Along with other modules, the proposed scheme is verified at system level using transaction level modeling (TLM) technique. Statistical results show that synchronization buffer of larger block size provides higher memory efficiency, less access cycles and power dissipation. However, the granularity of 8x8 block size provides better trade-off among cost, efficiency, power, and real-time requirement.
URI: http://dx.doi.org/10.1109/TCE.2007.339527
http://hdl.handle.net/11536/11202
ISSN: 0098-3063
DOI: 10.1109/TCE.2007.339527
期刊: IEEE TRANSACTIONS ON CONSUMER ELECTRONICS
Volume: 53
Issue: 1
起始頁: 209
結束頁: 217
Appears in Collections:Articles


Files in This Item:

  1. 000245420800036.pdf