Title: Impact of high-k offset spacer in 65-nm node SOI devices
Authors: Ma, Ming-Wen
Wu, Chien-Hung
Yang, Tsung-Yu
Kao, Kuo-Hsing
Wu, Woei-Cherng
Wang, Shui-Jinn
Chao, Tien-Sheng
Lei, Tan-Fu
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
Keywords: fringing electric field;high-k offset spacer dielectric;silicon-on-insulator (SOI)
Issue Date: 1-Mar-2007
Abstract: In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
URI: http://dx.doi.org/10.1109/LED.2007.891282
ISSN: 0741-3106
DOI: 10.1109/LED.2007.891282
Volume: 28
Issue: 3
Begin Page: 238
End Page: 241
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