標題: Impact of high-k offset spacer in 65-nm node SOI devices
作者: Ma, Ming-Wen
Wu, Chien-Hung
Yang, Tsung-Yu
Kao, Kuo-Hsing
Wu, Woei-Cherng
Wang, Shui-Jinn
Chao, Tien-Sheng
Lei, Tan-Fu
電子物理學系
電子工程學系及電子研究所
Department of Electrophysics
Department of Electronics Engineering and Institute of Electronics
關鍵字: fringing electric field;high-k offset spacer dielectric;silicon-on-insulator (SOI)
公開日期: 1-三月-2007
摘要: In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
URI: http://dx.doi.org/10.1109/LED.2007.891282
http://hdl.handle.net/11536/11075
ISSN: 0741-3106
DOI: 10.1109/LED.2007.891282
期刊: IEEE ELECTRON DEVICE LETTERS
Volume: 28
Issue: 3
起始頁: 238
結束頁: 241
顯示於類別:期刊論文


文件中的檔案:

  1. 000245184700017.pdf