標題: Parallel pixel processing using programmable gate arrays
作者: Budgett, DM
Tang, PE
Sharp, JH
Chatwin, CR
Young, RCD
Wang, RK
Scott, BF
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: programmable logic devices;image processing;parallel algorithms
公開日期: 15-Aug-1996
摘要: A reconfigurable hardware design permits very fast feature extraction from high frame rate video images. By implementing parallel pixel processing paths in programmable gate arrays, a wide range of image processing algorithms can be implemented in realtime.
URI: http://hdl.handle.net/11536/1105
ISSN: 0013-5194
期刊: ELECTRONICS LETTERS
Volume: 32
Issue: 17
起始頁: 1557
結束頁: 1559
Appears in Collections:Articles


Files in This Item:

  1. A1996VF33600023.pdf