Title: Delayed precise invalidation - A software cache coherence scheme
Authors: Hwang, TS
Lu, NP
Chung, CP
交大名義發表
資訊工程學系
National Chiao Tung University
Department of Computer Science
Keywords: cache coherence;compilers;invalidation
Issue Date: 1-Sep-1996
Abstract: Software cache coherence schemes are very desirable in the design of scalable multiprocessors and massively parallel processors. The authors propose a software cache coherence scheme named 'delayed precise invalidation' (DPI). DPI is based on compiler-time markings of references and a hardware local invalidation of stale data in parallel and selectively. With a small amount of additional hardware and a small set of cache management instructions, this scheme provides more cacheability and allows invalidation of partial elements in an array, overcoming some inefficiencies and deficiencies of previous software cache coherence schemes.
URI: http://hdl.handle.net/11536/1073
ISSN: 1350-2387
Journal: IEE PROCEEDINGS-COMPUTERS AND DIGITAL TECHNIQUES
Volume: 143
Issue: 5
Begin Page: 337
End Page: 344
Appears in Collections:Articles


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  1. A1996VP48100014.pdf