標題: A robust and fast digital background calibration technique for pipelined ADCs
作者: Fan, Jen-Lin
Wang, Chung-Yi
Wu, Jieh-Tsorng
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: analog-to-digital (A/D) conversion;calibration;digital background calibration;mixed analog-digital integrated circuits
公開日期: 1-Jun-2007
摘要: This paper presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust and has short calibration time. For a switched-capacitor (SC) pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC's signal path, and then calibration data can be extracted from the ADC's digital output without interrupting its normal conversion operation. Using an input-dependent scheme to generate the calibration random sequence, no additional signal range is required to accommodate the extra calibration signal. Furthermore, using random choppers to scramble signal can ensure that all necessary calibration data can be collected within a given time regardless of input conditions, resulting in a more robust ADC. A split-channel ADC architecture is proposed to reduce the calibration time. The split-channel ADC consists of two A/D channels that receive the same analog input but employ different random sequences for calibration. The calibration time can be greatly reduced by comparing the digital outputs from both channels and then removing the embedded perturbations before extracting the calibration data. The proposed calibration techniques are analyzed by using both theoretical formulation and system-level simulation.
URI: http://dx.doi.org/10.1109/TCSI.2007.895231
http://hdl.handle.net/11536/10714
ISSN: 1549-8328
DOI: 10.1109/TCSI.2007.895231
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Volume: 54
Issue: 6
起始頁: 1213
結束頁: 1223
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