標題: Method of combining multilevel memory cells for an error correction scheme
作者: Wu, Jieh-Tsorng
Wang, Ta-Hui
Chang, Hsie-Chia
公開日期: 19-Jan-2006
摘要: A memory combines plural memory cells for storing data wherein the differential stages voltage levels of memory cells are not limited in square value of 2 and can be improved linearly. The feature of the present invention can also increase memory capacity without increasing memory area. Furthermore it can remain voltage levels which cannot express 0 and 1 combination for error erasure messages when data is read. For efficient usage of memory, the increased memory capacity is not only for storing data but also for storing error correction scheme to assure the veracity of the storing data and improve producing yield and reliability for multilevel memory systems.
官方說明文件#: H03M013/00
URI: http://hdl.handle.net/11536/105715
專利國: USA
專利號碼: 20060015793
Appears in Collections:Patents


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  1. 20060015793.pdf