標題: Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
作者: Ker, MD
Wu, CY
Cheng, T
Chang, HH
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
公開日期: 1-九月-1996
摘要: Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed, The coupling capacitor is realized by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. A timing-original design model has been derived to calculate the capacitor-couple efficiency of this proposed ESD protection circuit, Using this capacitor-couple ESD protection circuit, the thinner gate oxide of CMOS devices in deep-submicron low-voltage CMOS ASIC can be effectively protected.
URI: http://dx.doi.org/10.1109/92.532032
http://hdl.handle.net/11536/1053
ISSN: 1063-8210
DOI: 10.1109/92.532032
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 4
Issue: 3
起始頁: 307
結束頁: 321
顯示於類別:期刊論文


文件中的檔案:

  1. A1996VE01800002.pdf