標題: Method for estimating capacitance weight errors and successive approximation analog to digital converter using the same
作者: Hong Hao-Chiao
Hsieh Tsung-Yin
公開日期: 9-Dec-2014
摘要: A successive approximation (SA) analog-to-digital converter (ADC) capable of estimating its own capacitance weight errors includes a comparator, a capacitor set, a switch set and a controller. The capacitor set includes a primary capacitor array including a plurality of binary-weighted capacitors, and a secondary capacitor array including a plurality of binary-weighted capacitors with known capacitance weights. The controller controls the switch set and repeats the steps of pre-charging the primary capacitor array, redistributing electric charges to the primary capacitor array and the secondary capacitor array, and performing a successive approximation binary searching on the primary capacitor array and the secondary capacitor array to calculate the capacitance weight error of each capacitor in the primary capacitor array. The calculated capacitance weight errors are used for calibrating the output of the successive approximation ADC.
官方說明文件#: H03M001/06
H03M001/12
H03M001/46
H03M001/10
URI: http://hdl.handle.net/11536/104322
專利國: USA
專利號碼: 08907826
Appears in Collections:Patents


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  1. 08907826.pdf