|標題:||Effect of Single Grain Boundary Position on Surrounding-Gate Polysilicon Thin Film Transistors|
Huang, Jung Y.
Institute of Communications Engineering
|關鍵字:||Surrounding-gate;Polysilicon TFT;Position of single grain boundary;Calibrated trap model parameters;Device-circuit mixed-mode simulation|
|摘要:||In this paper, single-grain-boundary-position-induced electrical characteristic variations in 300 nm surrounding-gate (i.e, gate-all-around, GAA) polysilicon thin film transistors (TFTs) are numerically investigated. For a 2T1C active-matrix circuit, a three-dimensional device-circuit coupled mixed-mode simulation shows that the switching speed of GAA TFT can be improved by nine times, compared with the result of the circuit using single-gate (SG) polysilicon TFTs. The position of single grain boundary near the drain side has an ill effect on device performance, but the influence can be suppressed in the GAA polysilicon TFTs. We found that under the same threshold voltage, the variation of threshold voltage can be reduced from 15 % to 5 %, with varying of gate structures of the GAA polysilicon TFT.|
|期刊:||2007 7TH IEEE CONFERENCE ON NANOTECHNOLOGY, VOL 1-3|
|Appears in Collections:||Conferences Paper|
Files in This Item: