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dc.contributor.authorChang, Kow Mingen_US
dc.contributor.authorLin, Gin Minen_US
dc.contributor.authorYang, Guo Liangen_US
dc.date.accessioned2014-12-08T15:13:26Z-
dc.date.available2014-12-08T15:13:26Z-
dc.date.issued2007-09-01en_US
dc.identifier.issn0741-3106en_US
dc.identifier.urihttp://dx.doi.org/10.1109/LED.2007.903313en_US
dc.identifier.urihttp://hdl.handle.net/11536/10381-
dc.description.abstractIn this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower OFF-state current (177 to 6.29 nA), and the ON/OFF current ratio is only slightly decreased from 1.71 x 10(7) to 1.39 x 10(7). Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.en_US
dc.language.isoen_USen_US
dc.subjectdamascene processen_US
dc.subjectfour masksen_US
dc.subjecton/off current ratioen_US
dc.subjectpolycrystalline silicon thin-film transistor (poly-Si TFT)en_US
dc.subjectraised source/drain (RSD)en_US
dc.subjectself-aligned gateen_US
dc.subjectthin channelen_US
dc.titleNovel low-temperature polysilicon thin-film transistors with a self-aligned gate and raised source/drain formed by the damascene processen_US
dc.typeArticleen_US
dc.identifier.doi10.1109/LED.2007.903313en_US
dc.identifier.journalIEEE ELECTRON DEVICE LETTERSen_US
dc.citation.volume28en_US
dc.citation.issue9en_US
dc.citation.spage806en_US
dc.citation.epage808en_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.identifier.wosnumberWOS:000249023500009-
dc.citation.woscount4-
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