Design of GI Image Signal Processor for Capsule Endoscopy
|關鍵字:||影像壓縮;膠囊內視鏡;視網膜晶片;功率意識;Image compression;capsule endoscopy;retina circuit;power-aware architecture|
The objective of this project is to develop a power-aware image processor for capsule endoscopy or swallowable imaging capsules. The image processor consists three parts: disease target detector, image sensor, and image compressor. In applications of capsule endoscopy, it is imperative to consider battery life/performance trade-offs. Applying state-of-the-art video compression techniques may significantly reduce the image bit rate by their high compression ratio, but they all require intensive computation and consume much power from battery. There are many fast compression algorithms for reducing computation load; however, they may result in distoration of original image, which is not good for the use of medical care. Furthermore, the imaging capsules will travel in alimentary canal for three hours. Enabling all functions of the image processor over the three-hour trip will limit the functionality and resolution of image processing because of insufficient battery power. Hence, this project aims on three objectives: detection of diagnosing target, ultra-low-power gastrointestinal (GI) image compression, and power-aware architecture. First of all, this project will apply the retinal processing circuit for the disease target detection. The retinal processing circuit features high dynamic range, low power, and high sensitivity to motion object. These features make the capsule endoscopy able to operate in the dim canal initially, with part of lights. When sensing the targets, the endoscopy will turn on all the lights and the image processing circuits. Secondly, this project will simplify traditional video compression algorithms as per the characteristics of GI image. With a specific scanning on the CMOS sensor, we will propose a scalable compression algorithm for the later power-stepping technique. Finally, we will develop a power-aware architecture for battery-life extension. The power-aware architecture is an architecture that can properly reduce the computation load as the battery status changed while the qulity degradation is little. In the project, we will consider not only the minimization of average power dissipation but transient characteristics of power dissipation, such as peak power and power gradient or differential.
|Appears in Collections:||Research Plans|