Title: 以極少數奈米晶粒為電荷存取中心之矽奈米線非揮發記憶元件研究
Study of Silicon Nanowire Nonvolatile Memory with Few Nanocrystals as Charge Storage Centers
Authors: 許鉦宗
Keywords: 電子束微影;自組裝沉積;絕緣矽;矽奈米線;矽奈米線非揮發記憶元件;穿隧現象;多階電荷儲存;E-beam lithography;SOI;Self-assembly technique;silicon nanowires;silicon nanowire nonvolatile memory;multiple-level charge storage;multiple-bit;channel hot electron tunneling;Folwer-Nordheim tunneling
Issue Date: 2008
Abstract: 非揮發性記憶(nonvolatile memory)元件主要必須符合高可靠度(reliability)、低功率消耗(power consumption)、與低工作電壓(working voltage)等等特性。由於元件尺寸快速奈米化,即使以分散電荷儲存的SONOS結構也面對了兩個彼此trade-off問題: 較長記憶儲存時間與更高存取速率。本研究擬利用電子束微影(E-beam Lithography)與自組裝(self-assembly)沉積技術在(100)絕緣矽(SOI)矽晶基材上研製矽奈線非揮發記憶元件。奈米線非揮發記憶元件的主結構是用電子束微影將圖形轉換至top silicon上形成奈米級矽結構,並以此奈米級矽結構產生矽奈米線做為矽奈米線非揮發記憶元件之基礎。另外、利用自組裝沉積AEAPTMS或MPTMS單層分子膜於二氧化矽上,將奈米金屬粒子或是半導體量子點(CdSe等)選擇性沉積在分子層上。結合上述兩個技術與元件製程技術,便可以研製以奈米金粒子或是半導體量子點為電荷儲存中心的奈米非揮發記憶元件。本計畫將於不同溫度(4.2K~450K) 下,經由變溫I-V/C-V量測,觀察矽奈米線非揮發記憶元件的存取穩定性、電流/電壓特性、不同program/erase的穿隧現象如channel hot electrons或Folwer-Nordheim等將元件特性最佳化。另外、經由沉積多種或多層奈米金屬粒子或是半導體量子點,來達成多階電荷儲存(Multiple-level charge storage)或多位元(multiple-bit)的元件也一併加以研製探討。最後、本研究將於第三年將研製單個(或數個) 奈米金屬粒子或是半導體量子點做為懸浮閘的矽奈米線非揮發記憶元件,並建立相關理論模型。
Modern nonvolatile semiconductor memories possess properties like reliable, low-power, low-voltage performance. There are essentially two dominant technologies which compete for an ever-expanding world market: floating-gate EEPROMs and floating-trap SONOS. To date, the mass produced nonvolatile memory devices are based on the concept of a continuous layer of floating gate. However, it has faced the difficulties of consecutive scaling down due to the compromise between long-term nonvolatility and high operating speed. This research project focuses on modeling, fabrication and measurement of silicon nanowire nonvolatile memory devices on (100) SOI silicon wafer. The main structure of a nano nonvolatile device is fabricated with E-beam lithography (EBL); the e-beam patterns are transferred into silicon via dry etching to generate silicon nanowires (SiNWs). On the other hand, self-assembly technique using AEAPTMS or MPTMS monolayers as a linker to attract nanoparticles or semiconductor quantum dots on the silicon dioxide surface on the selective area of SiNWs. Integration of these two techniques described above, silicon nanowire nonvolatile memory device with metal nanoparticles or quantum dots as charge storage centers can be achieved. Retention time, electrical properties, and different tunneling phenomena like channel hot electron and Folwer-Nordheim of nano nonvolatile devices will all be observed and investigated via variable temperature I-V/C-V measurements. Multiple-level charge storage and multiple-bit structures will also investigated. At the third year, silicon nanowire nonvolatile memory devices functioning with single or few nanopraticles (quantum dots) as floating gates will be demonstrated and related model will be constructed.
Gov't Doc #: NSC97-2221-E009-157-MY3
URI: http://hdl.handle.net/11536/102845
Appears in Collections:Research Plans