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dc.contributor.author李育民en_US
dc.contributor.authorLEE YU-MINen_US
dc.date.accessioned2014-12-13T10:51:38Z-
dc.date.available2014-12-13T10:51:38Z-
dc.date.issued2008en_US
dc.identifier.govdocNSC97-2220-E009-003zh_TW
dc.identifier.urihttp://hdl.handle.net/11536/102828-
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1690537&docId=291660en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.language.isozh_TWen_US
dc.title先進製程技術之設計與可靠度提昇研究---子計畫二:考慮製程變異的導線模型、時序分析以及最佳化(III)zh_TW
dc.titleProcess Variations Aware Interconnect Modeling, Timing Analysis and Optimization(III)en_US
dc.typePlanen_US
dc.contributor.department國立交通大學電信工程學系(所)zh_TW
Appears in Collections:Research Plans