標題: 先進可選性高鏡像抑制CMOS射頻接收機架構
Advanced Reconfigurable CMOS RF Receiver Architecture with High Image Rejection Ratio
作者: 孟慶宗
MENG CHINCHUN
國立交通大學電信工程學系(所)
關鍵字: 射頻積體電路;威福哈特力接收機;應用LO 延遲補償的混頻器;雙頻帶;50%責任週期;除頻器;radio frequency integrated circuits;Weaver-Hartley receiver;Gilbert mixerusing the LO time delay compensated cell;dual band;50% duty cycle;divider
公開日期: 2008
摘要: 隨著矽製程技術的進步,一日千里,CMOS 主導了整個射頻通信積體電路的發 展。因為CMOS 的電晶體截止頻率越來越高,通信系統單晶片的趨勢已越來越明 顯。本計劃將應用矽製程技術來開發高性能之射頻通訊積體電路,以求提供系統整 合之解決方案。 在整個射頻通訊系統架構中,接收器架構佔了很重要的地位,尤其是對於鏡像 抑制的能力就非常重要,因此在此計畫中,我們將針對創新的威福哈特力接收機系 統分析與設計,並對於每一部份的電路如混頻器、正交相位產生器、50%責任週期 雙頻帶本地震盪訊號、以及電晶體元件特性做研究分析,如此一來,便可設計出高 鏡像抑制的接收機系統,最後,我們將把此系統設計、應用在雙頻帶的通訊系統中, 表現出其實用性與高效能特性。 計畫工作內容如下: 1.分析矽製程技術的吉伯特混頻器的隔絕度特性, 2.設計與實作運用LO 延遲補償電路的高性能矽製程技術吉伯特混頻器, 3.設計與實作創新的Weaver-Hartley 的鏡像抑制接收器, 4.設計與實作創新雙頻帶的Weaver-Hartley 的鏡像抑制接收器, 5.設計與實作創新雙頻帶頻率產生器, 6.建立鏡像抑制接收器自動化量測環境。
As the silicon-based technologies improve rapidly, the CMOS technology dominates the development of the RFIC. The CMOS transistor has higher and higher cut-off frequency and thus the communication SOC in CMOS is the trend. We will focus on developing the high performance RFIC using the silicon technologies in order to provide a solution to the system-on-chip. A receiver architecture plays an important role in the overall radio frequency communication system for image rejection. Therefore, our research topic is the analysis and design of novel Weaver-Hartley image rejection receivers. In addition, we work on transistor characteristics and each circuit such as mixers, quadrature generators, and 50% duty-cycle dual frequency generators. After the study, the receiver with high image rejection ratio is proposed and realized. Finally, this receiver architecture will be designed and applied for the dual-band communication system to reveal its practicability and high performance. The highlights of the research are summarized here. 1. Characterization and analysis of the isolation property of the silicon based Gilbert mixer. 2. Design and implementation of the high performance silicon based Gilbert mixer with LO time delay compensation stage. 3. Design and implementation of the novel Weaver-Hartley receiver. 4. Design and implementation of the dual-band Weaver-Hartley receiver. 5. Design and implementation of the dual-band frequency generator with 50% duty-cycle outputs. 6. Set-up and automation of the measurements for the image rejection system.
官方說明文件#: NSC97-2221-E009-171
URI: http://hdl.handle.net/11536/102767
https://www.grb.gov.tw/search/planDetail?id=1688181&docId=291116
Appears in Collections:Research Plans


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