標題: 高速序列傳輸電路之自我測試設計、實作、與分析
BIST Design, Implementation, and Analysis for High Speed Serial I/O
作者: 蘇朝琴
SU CHAU-CHIN
國立交通大學電機與控制工程學系(所)
關鍵字: 高速序列傳輸;自我測試;鎖相迴路;傳輸接收器;混合信號電;High Speed Serial I/O;Built-in Self Test;Phase Locked Loop;Tranceiver;Mixed Signal Circuit.
公開日期: 2008
摘要: 本計劃的主要內容在針對高速序列傳輸的自我測試技術,做一個完整的設計,以及透徹的分析。一個高速序列傳輸電路包括有三個重要的模組,鎖相迴路、傳輸器、接收器。這三個模組的自我測試各有不同的重點。鎖項迴路的模組,主要在於時脈抖動的量測,因為這個部份必須達到PS的準確度,這個部份我們已經有初步的結果。在傳輸電路的自我測試上,主要在於眼狀圖眼開 (Eye Opening) 的量測,這裡有兩項工作,一是眼緣 (Eye Transition Edge) 的抖動量測,二是眼高的量測。前一項我們採用數位的方式量測以減少不準度與硬體設計的難度,後者我們將改進我們在ASPDAC 2003邀稿論文中的方法以應用於高速。在接收器的自我測試上則以Jitter Injection Filter 為重點,如何有效而且在管控下控制眼狀圖的眼開大小,這樣我們才能夠測試接收器對信號整合度(Signal Integrity) 的容忍程度。當三個模組整合起來以後,最為經濟的方法就是迴授錯誤率的測試 (Loop Back Bit Error Rate Test) 。然而這個方法有許多缺陷,例如他無法測知與規格的間的差距,以推估測試的餘域 (Margin)。在此,我們計畫根據前三者所量到的數據,推算BER的餘域,如此才能真正的使用於實際測試上。 本計劃預計在三年後,設計一個5~6Gbps的LVDS傳輸接收電路。針對鎖相迴路、傳輸器、接收器我們將各設計一個合適的自我測試模組。整體傳輸接收器部分,我們將設計一個迴授位元錯誤率的測試模組。最後,我們將交叉比對測試結果,推導出一個實際的位元錯誤率與眼開餘域的關係。基本上,我們希望透過實作與實測來做為推導的依據,修正公式推導的盲點,而非以純數學的方式來推導公式,畢竟在PS的領域內,所有的公式推導會面臨到非線性電路特性的極限,就如同奈米級電路設計一般。 (本團隊已經有5Gbps Transmitter、2.5GHz PLL、2.5Gbps CDR、PS抖動量測的能力,詳見計畫書內容)
The purpose of this research is to design, implement, and analyze a built-in self test (BIST) circuits for high speed serial I/O. A high speed serial I/O contains three major building blocks, a phase-locked loop, a transmitter, and a receiver. For PLL BIST, the major issue is the jitter measurement. The difficulty is to achieve PS resolution. Here, we already have some experiences and will be presented later. For Transmitter BIST, the major issue is the eye diagram measurement. An eye opening includes the jitter at the eye edge transition and height of the eye. For the jitter measurement, we will take a digital approach to minimize the hardware overhead. For the height measurement, we will modify the technique proposed in an ASPDAC 2003 invited paper to be used in a high speed environment. For the Receiver BIST, the major issue is the jitter injection and attenuation filter. One must be able to control precisely the attenuation and jitter in order to test the receiver』s tolerance on the signal integrity. For the Tranceiver BIST, the most cost effective method is the loop-back bit error rate test method. However, this method can not provide the information on how much the test margin. The margin is an important information for the reliability consideration. Here, we would like to derive the relationship between the above three physically measured data and theoretical aspect of the BER. With which, one is able to apply BER test with confidence. This three-year research project is expected to produce a 5~6Gbps transceiver with BIST. For PLL, transmitter, and receiver, we will design a BIST circuit for the jitter, eye opening, and signal integrity tolerance measurement. For the transceiver, we will derive mathematically the relationship between BER and physically measured data. Basically, we would like to derive mathematical model based on physical measurement instead of pure mathematical derivation. After all, when a timing approaching PS range, the circuit will encounter all sort of nonlinearities, just like the nanometer circuit design.
官方說明文件#: NSC95-2221-E009-328-MY3
URI: http://hdl.handle.net/11536/102234
https://www.grb.gov.tw/search/planDetail?id=1595458&docId=273843
Appears in Collections:Research Plans