標題: An ultra-low-power and portable digitally controlled oscillator for SoC applications
作者: Sheng, Duo
Chung, Ching-Che
Lee, Chen-Yi
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
關鍵字: all-digital phase-locked loop (ADPLL);cell-based design;digitally controlled oscillator (DCO);hysteresis delay cell (HDC);portable;segmental delay line (SDL)
公開日期: 1-十一月-2007
摘要: In this paper, a novel ultra-low-power digitally controlled oscillator (DCO) with cell-based design for system-on-chip (SoC) applications is presented. Based on the proposed segmental delay line (SDL) and hysteresis delay cell (HDC), the power consumption can be saved by 70% and 86.2% in coarse-tuning and fine-tuning stages, respectively, as compared with conventional approaches. Besides, the proposed DCO employs a cascade-stage structure to achieve high resolution and wide range at the same time. Measurement results show that power consumption of the proposed DCO can be improved to 140 mu W (@200 MHz) with 1.47-ps resolution. In addition, the proposed DCO can be implemented with standard cells, making it easily portable to different processes and very suitable for SoC applications.
URI: http://dx.doi.org/10.1109/TCSII.2007.903782
http://hdl.handle.net/11536/10141
ISSN: 1549-7747
DOI: 10.1109/TCSII.2007.903782
期刊: IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS
Volume: 54
Issue: 11
起始頁: 954
結束頁: 958
顯示於類別:期刊論文


文件中的檔案:

  1. 000250992300006.pdf