標題: A design-for-digital-testability circuit structure for Sigma-Delta modulators
作者: Hong, Hao-Chiao
電控工程研究所
Institute of Electrical and Control Engineering
關鍵字: analog-to-digital converter (ADC);design-for-testability (DFT);digitally testable;mixed-signal circuit testing;Sigma-Delta modulator
公開日期: 1-Dec-2007
摘要: A design-for-digital-testability (DfDT) switched-capacitor circuit structure for testing Sigma-Delta modulators with digital stimuli is presented to reduce the overall testing cost. In the test mode, the DfDT circuits are reconfigured as a one-bit digital-to-charge converter to accept a repetitively applied Sigma-Delta modulated bit-stream as its stimulus. The single-bit characteristic ensures that the generated stimulus is nonlinearity free. In addition, the proposed DfDT structure reuses most of the analog components in the test mode and keeps the same loads for the operational amplifiers as if they were in the normal mode. It thereby achieves many advantages including lower cost, higher fault coverage, higher measurement accuracy, and the capability of performing at-speed tests. A second-order Sigma-Delta modulator was designed and fabricated to demonstrate the effectiveness of the DfDT structure. Our experimental results show that the digital test is able to measure a harmonic distortion lower than -106 dBFS. Meanwhile, the dynamic range measured with the digital stimulus is as high as 84.4 dB at an over-sampling ratio of 128. The proposed DfDT scheme can be easily applied to other types of Sigma-Delta modulators, making them also digitally testable.
URI: http://dx.doi.org/10.1109/TVLSI.2007.909799
http://hdl.handle.net/11536/10074
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2007.909799
期刊: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 15
Issue: 12
起始頁: 1341
結束頁: 1350
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