標題: 應用於多視角立體視訊之多核心節能智慧超微型通訊系統研究---總計畫(I)
Multi-Core Femtocell Communication Systems for Multi-View 3-D Video(I)
作者: 張添烜
Chang Tian-Sheuan
國立交通大學電子工程學系及電子研究所
關鍵字: 多核心;以記憶體為重心;晶內資料傳輸;節能效益;超微型基地台;16×16多輸入多輸出;多視角3D視訊
公開日期: 2010
摘要: 因應行動多媒體服務在「數量」與「畫質」需求的持續擴張,多視角3D 視訊技術成為全球多媒體 產業的未來之星,同時,過去以大型基地台為主的行動通訊架構已逐漸無法滿足使用者的需求,,超 微型基地台興起以熱點佈建(Hot-Spot Deployment)來省卻大型基地台並滿足傳輸覆蓋範圍之需求。因 此,本計畫將針對節能多媒體智慧超微型通訊系統提供多串流寬頻立體視訊服務之應用,透過最佳化 的方式,開發一套具能源效益的可重置多核心運算平台。此超微型通訊系統上須有效解決高畫質多視 角立體視訊處理所需的龐大運算,並提供足夠頻寬的多使用者的傳輸服務。故所開發之多核心平台應 具備可同時處理「多視角立體視訊」、「多串流多模式低干擾網路管理」與「可重置多串流多天線無線 訊號處理」,並提供總頻寬至少3G bps 的多媒體服務,此外平台也針對「應用特性」做以「記憶體儲 存為中心」之可重置化的高可靠度多核心傳輸管理與資源最佳化,藉由階層式記憶體管理及功率控 管,並結合跨階層的軟硬共同設計達至系統效能的最佳化。
With the accelerated progress in video sizes and quality of mobile multimedia services, multi-view 3D video, is now regarded as the future star in global multimedia industry. The conventional macro base stations designed for wide service coverage cannot meet the increasing demands in 3D high-quality transmission especially for indoor applications. The emerging Femtocell with wire-line backhaul has been proposed as one of the key deployment architectures in 4G wireless systems to achieve 1 Gbps transmission rates. In order to meet these future transmission challenges and to support multiple wideband 3D video streaming services, this project will develop an energy efficient reconfigurable multi-core platform for intelligent multimedia femtocell systems. This multimedia femtocell is expected to support massive computation for high definition multi-view 3D video and to provide intelligent resource allocation schemes for achieving multi-user high-quality transmission without interfering by other macrocell base stations or self-deployed femtocells. Furthermore, beyond 4G requirements, an over 3 Gbps transmission platform, based on reconfigurable multi-streaming multi-antenna wireless signal processing and multi-mode multi-streaming resource controls, will be developed. Finally, including hierarchical memory management, the power control, and cross layer hardware/software co-design, this multi-core platform will be able to optimize the application-specific interconnection performance through the reconfigurable memory centric and fault tolerant system designs.
官方說明文件#: NSC99-2221-E009-189
URI: http://hdl.handle.net/11536/100674
https://www.grb.gov.tw/search/planDetail?id=2110031&docId=336953
顯示於類別:研究計畫


文件中的檔案:

  1. 992221E009189.PDF