標題: 內嵌矽奈米點之SONOS記憶體元件
Embedded Silicon Nano-Crystal SONOS Memories
作者: 趙天生
CHAO TIEN-SHENG
國立交通大學電子物理學系(所)
公開日期: 2010
摘要: 本計畫以研究多晶矽-氧化層-氮化矽-氧化層-半導體記憶體元件為主要方向,第 一部分為記憶體元件、薄膜電晶體、合金金屬矽化物及矽奈米線電晶體之整合型研究, 利用合金金屬矽化物的技術去製造具高性能且高可靠度之二位元多晶矽薄膜電晶體非 揮發記憶體。此外,我們也將設法建立新式、簡單之新穎矽奈米線薄膜電晶體,並針對 此矽奈米線薄膜電晶體作特性及可靠度的分析。第二部分則是研究如何製作矽奈米點嵌 入氮化矽絕緣層中之記憶體元件,根據我們先前的研究可以發現矽奈米點成長在氮化矽 上的密度將會大於成長在二氧化矽上,因此,我們可以利用較高密度的矽奈米點製作出 高密度的記憶體元件。之後我們將改變矽奈米點存在於氮化矽的位置,並討論不同的矽 奈米點位置如何影響記憶體元件的特性。此外,我們將研究以高介電材料來當元件的阻 擋氧化層以及功函數較高的金屬搭配矽奈米點記憶體元件的特性,我們相信高介電材料 的阻擋氧化層以及功函數高的金屬可以有效克服記憶體抹除飽和的問題。第三部分則是 針對選擇性隱藏式閘極記憶體作一研究與探討,我們將嘗試以動態臨限電壓操作法的寫 入方式應用於隱藏性選擇式閘極結構的記憶體元件,估計此操作方式可以有效地降低元 件的操作電壓同時也提升元件的寫入效能,使本計劃中的元件可以達到高效能且符合低 功率消耗的未來趨勢;另外也將針對動態臨限電壓操作法做一些模擬的探討以釐清其寫 入機制。而我們也會討探討NAND 型記憶體陣列結構在多位元操作模式下之各項特性 與可靠度,最後將會同時研究NAND 型與NOR 型選擇性隱藏式閘極記憶體陣列結構在 每單元胞儲存二位元中對第二位元讀取效應。
The novel SONOS memory will be investigated in this work. At first, the integration of SONOS memory, TFT, silicide technique and Si nano-wire transistor will be studied. The 2-bit Poly-Si-TFT Nonvolatile Memory will be demonstrated by using silicide technique in order to achieve high performance and good reliability of SONOS memory. In addition, we’ll try to find the simple fabrication of Si nano-wire SONOS memory. Then, the characteristics and reliability of novel Si nano-wire SONOS memory will be discussed. Second, the SONOS memory fabrication of Si nano-dots embedded in SiN dielectric will be studied. According to our previous research, the density of Si nano-dots deposited on SiN will be large than deposition on SiO2. As a result, the high density Si nano-dots SONOS memory can be achieved owing to plenty Si nano-dots. Then, we’ll study how to control the distribution of Si nano-dots in SiN dielectric, and how the characterization of Si nano-dots SONOS memory is affected by Si nano-dots distribution. Besides, the Si nano-dots SONOS memory with high-k blocking dielectric and high work function metal gate will be studied. We believe the high-k blocking dielectric and high work function metal gate can avoid overerasure of charge storage flash memory cell. The third part is investigation of novel wrapped-select-gate (WSG) SONOS memory. We’ll try to use the dynamic threshold (DT) voltage method in programming application for WSG-SONOS memory. This operation method may reduce the operation voltage and enhance the programming efficiency to achieve the low power consumption target. In addition, we’ll do some simulation to find the clear mechanism of DT-operation in WSG-SONOS memory. Furthermore, the multi-level operation and reliability issue of NAND WSG-SONOS memory will be discussed. Finally, the second bit effect of both NAND and NOR type WSG-SONOS memory will be characterized.
官方說明文件#: NSC97-2221-E009-152-MY3
URI: http://hdl.handle.net/11536/100316
https://www.grb.gov.tw/search/planDetail?id=1982294&docId=323262
顯示於類別:研究計畫


文件中的檔案:

  1. 972221E009152MY3(第1年).PDF
  2. 972221E009152MY3(第2年).PDF
  3. 972221E009152MY3(第3年).PDF