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Issue DateTitleAuthor(s)
1-Aug-2015A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power ApplicationsChang, Chia-Wen; Chu, Yuan-Hua; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-2012A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing TracingTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Lu, Chien-Yu; Lin, Yuh-Jiun; Wang, Meng-Hsueh; Huang, Huan-Shun; Lee, Kuen-Di; Shih, Wei-Chiang (Willis); Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011超低功耗次臨界操作靜態隨機存取記憶體的設計與實現杜明賢; Tu, Ming-Hsien; 周世傑; Jou, Shyh-Jye; 電子研究所
2012低功率低電壓之資料處理單元設計王儷蓉; Wang, Li-Rong; 周世傑; Jou, Shyh-Jye; 電子工程學系 電子研究所
1-Dec-2010Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-AssistTu, Ming-Hsien; Lin, Jihi-Yu; Tsai, Ming-Chien; Jou, Shyh-Jye; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2016A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression TechniquesChang, Chia-Wen; Lo, Kai-Yu; Ibrahim, Hossameldin A.; Su, Ming-Chiuan; Chu, Yuan-Hua; Jou, Shyh-Jye; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics