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公開日期標題作者
2007A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaverWong, Cheng-Chi; Tang, Cheng-Hao; Lai, Ming-Wei; Zheng, Yan-Xiu; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; Su, Yu-T.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Lee, Yung-Yu; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2012A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual TrellisLin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-十一月-2013A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual TrellisLin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-一月-2015An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo DecoderLin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-六月-2011High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP InterleaverWong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010A Multiple Code-Rate Turbo Decoder Based on Reciprocal Dual Trellis ArchitectureLin, Chen-Yang; Wong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-七月-2010Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE SystemWong, Cheng-Chi; Chang, Hsie-Chia; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-二月-2010Turbo Decoder Using Contention-Free Interleaver and Parallel ArchitectureWong, Cheng-Chi; Lai, Ming-Wei; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen-Yi; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2010運用平行架構及無競爭式交錯器之渦輪碼解碼器翁政吉; Wong, Cheng-Chi; 張錫嘉; Chang, Hsie-Chia; 電子研究所