Browsing by Author Wang, Tahui

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Issue DateTitleAuthor(s)
1-Jan-2018Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memoryLu, C. C.; Cheng, C. C.; Chiu, H. P.; Lin, W. L.; Chen, T. W.; Ku, S. H.; Tsai, Wen-Jer; Lu, T. C.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006<bold>Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory</bold>Gu, S. H.; Li, C. W.; Wang, Tahui; Lu, W. P.; Chen, K. C.; Ku, Joseph; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Cell Endurance Prediction from a Large-area SONOS CapacitorLee, C. H.; Tu, W. H.; Gu, S. H.; Wu, C. W.; Lin, S. W.; Yeh, T. H.; Chen, K. F.; Chen, Y. J.; Hsieh, J. Y.; Huang, I. J.; Zous, N. K.; Han, T. T.; Chen, M. S.; Lu, W. P.; Chen, K. C.; Wang, Tahui; Lu, C. Y.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jun-2006Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETsChan, Chien-Tai; Tang, Chun-Jung; Wang, Tahui; Wang, Howard C. -H.; Tang, Denny D.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
7-Dec-2017Characterization and modeling of SET/RESET cycling induced read-disturb failure time degradation in a resistive switching memorySu, Po-Cheng; Hsu, Chun-Chi; Du, Sin-I; Wang, Tahui; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
20-Aug-2012Characterization and modeling of trap number and creation time distributions under negative-bias-temperature stressChiu, Jung-Piao; Li, Chi-Wei; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memoryTang, Chun-Jung; Li, C. W.; Wang, Tahui; Gu, S. H.; Chen, P. C.; Chang, Y. W.; Lu, T. C.; Lu, W. P.; Chen, K. C.; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2004Characterization and SPICE Modeling of High Voltage LDMOS邵晉輝; Shao, Jin-huei; 汪大暉; Wang, Tahui; 電子研究所
17-Jul-2017Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal methodLiu, Yu-Heng; Jiang, Cheng-Min; Lin, Hsiao-Yi; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan; 電機學院; 電子工程學系及電子研究所; College of Electrical and Computer Engineering; Department of Electronics Engineering and Institute of Electronics
1-Jan-2018Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash MemoryLin, T. W.; Ku, S. H.; Cheng, C. H.; Lee, C. W.; Ijen-Huang; Tsai, Wen-Jer; Lu, T. C.; Lu, W. P.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Feb-2012A Comparative Study of NBTI and RTN Amplitude Distributions in High-kappa Gate Dielectric pMOSFETsChiu, J. P.; Chung, Y. T.; Wang, Tahui; Chen, Min-Cheng; Lu, C. Y.; Yu, K. F.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2018Correlation between SET-State Current Level and Read Disturb Failure Time in a Resistive Switching MemorySu, P. C.; Jiang, C. M.; Wang, C. W.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Feb-2015Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching MemoryChung, Yueh-Ting; Su, Po-Cheng; Cheng, Yu-Hsuan; Wang, Tahui; Chen, Min-Cheng; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2008Effects of length scaling on electromigration in dual-damascene copper interconnectsLin, M. H.; Lin, M. T.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-2007Effects of width scaling and layout variation on dual damascene copper interconnect electromigrationLin, M. H.; Chang, K. P.; Su, K. C.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006Effects of width scaling, length scaling, and layout variation on electromigrationin in dual damascene copper interconnectsLin, M. H.; Chang, K. P.; Su, K. C.; Wang, Tahui; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Jan-2017Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash MemoryLiu, Yu-Heng; Jiang, Cheng-Min; Chen, Wei-Chun; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
Jan-2017Electric Field Induced Nitride Trapped Charge Lateral Migration in a SONOS Flash MemoryLiu, Yu-Heng; Jiang, Cheng-Min; Chen, Wei-Chun; Wang, Tahui; Tsai, Wen-Jer; Lu, Tao-Cheng; Chen, Kuang-Chao; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2018Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash MemoryKu, S. H.; Lin, T. W.; Cheng, C. H.; Lee, C. W.; Chen, Ti-Wen; Tsai, Wen-Jer; Lu, T. C.; Lu, W. P.; Chen, K. C.; Wang, Tahui; Lu, Chih-Yuan; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013Estimating the Detection Stability of a Si Nanowire Sensor Using an Additional Charging ElectrodeChen, Min-Cheng; Chen, Hsiao-Chien; Lee, Ta-Hsien; Lin, Yu-Hsien; Shih, Jyun-Hung; Wang, Bo-Wei; Hou, Yun-Fang; Chen, Yi-Ju; Lin, Chia-Yi; Lin, Chang-Hsien; Hsieh, Yi-Ping; Ho, ChiaHua; Hua, Mu-Yi; Qiu, Jian-Tai; Wang, Tahui; Yang, Fu-Liang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics