Browsing by Author Jou, Jing-Yang

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Issue DateTitleAuthor(s)
2011Accelerating Dynamic Peak Power Analysis Using An Essential-Signal-Based MethodologyShih, Che-Hua; Yen, Chia-Chih; Lin, Shen-Tien; Lin, Hermes; Jou, Jing-Yang; 交大名義發表; National Chiao Tung University
1-Feb-2009Accurate Rank Ordering of Error Candidates for Efficient HDL Design DebuggingJiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2013Cache Capacity Aware Thread Scheduling for Irregular Memory Access on Many-Core GPGPUsKuo, Hsien-Kai; Yen, Ta-Kan; Lai, Bo-Cheng Charles; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2015A Cache Hierarchy Aware Thread Mapping Methodology for GPGPUsLai, Bo-Cheng Charles; Kuo, Hsien-Kai; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Chain-Based Pin Count Minimization for General-Purpose Digital Microfluidic BiochipsLei, Yung-Chun; Hsu, Chen-Shing; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008A code generation algorithm of crosstalk-avoidance code with memory for low-power on-chip busCheng, Kuang-Chin; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2005Communication-driven task binding for multiprocessor with latency insensitive Network-on-ChipLin, Liang-Yu; Wang, Cheng-Yeh; Huang, Pao-Jui; Chou, Chih-Chieh; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Design-for-Debug Layout Adjustment for FIB Probing and Circuit EditingChen, Kuo-An; Chang, Tsung-Wei; Wu, Meng-Chen; Chao, Mango C. -T.; Jou, Jing-Yang; Chen, Sonair; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Nov-2014Efficient Coverage-Driven Stimulus Generation Using Simultaneous SAT Solving, with Application to SystemVerilogCheng, An-Che; Yen, Chia-Chih (Jack); Val, Celina G.; Bayless, Sam; Hu, Alan J.; Jiang, Iris Hui-Ru; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Equivalence Checking of Scheduling with Speculative Code Transformations in High-Level SynthesisLee, Chi-Hui; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
28-Aug-2008Fine-grained bandwidth control arbiter and the method thereofHuang, Juinn-Dar; Lin, Bu-Ching; Lee, Geeng-Wei; Jou, Jing-Yang
1-Sep-2010FSM-Based Formal Compliance Verification of Interface ProtocolsShih, Che-Hua; Yang, Ya-Ching; Yen, Chia-Chih; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006FSM-based transaction-level functional coverage for interface compliance verificationSu, Man-Yun; Shih, Che-Hua; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Hierarchical Architecture for Network-on-Chip PlatformLin, Liang-Yu; Lin, Huang-Kai; Wang, Cheng-Yeh; Van, Lan-Da; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Aug-2007Hybrid word-length optimization methods of pipelined FFT processorsWang, Cheng-Yeh; Kuo, Chih-Bin; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Apr-2014ILP-Based Bitwidth-Aware Subexpression Sharing for Area Minimization in Multiple Constant MultiplicationLin, Bu-Ching; Huang, Juinn-Dar; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014A Learning-on-Cloud Power Management Policy for Smart DevicesPan, Gung-Yu; Lai, Bo-Cheng Charles; Chen, Sheng-Yen; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011Mixed Non-Rectangular Block Packing for Non-Manhattan Layout ArchitecturesWu, Meng-Chen; Chen, Hung-Ming; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Multiple-Fault Diagnosis Using Faulty-Region IdentificationTasi, Meng-Jai; Chao, Mango C. -T.; Jou, Jing-Yang; Wu, Meng-Chen; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Aug-2007Observability analysis on HDL descriptions for effective functional validationJiang, Tai-Ying; Liu, Chien-Nan Jimmy; Jou, Jing-Yang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics