Browsing by Author Hwang, Wei

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Issue DateTitleAuthor(s)
1-Dec-2012A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-AssistLu, Chien-Yu; Tu, Ming-Hsien; Yang, Hao-I; Wu, Ya-Ping; Huang, Huan-Shun; Lin, Yuh-Jiun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
20140.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOSHuang, Po-Tsang; Lai, Shu-Lin; Chuang, Ching-Te; Hwang, Wei; Huang, Jason; Hu, Angelo; Kan, Paul; Jia, Michael; Lv, Kimi; Zhang, Bright; 電機工程學系; Department of Electrical and Computer Engineering
2014A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SOCDhong, Sang; Guo, Richard; Kuo, Ming-Zhang; Yang, Ping-Lin; Lin, Cheng-Chung; Huang, Kevin; Wang, Min-Jer; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jul-2017A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-AssistWu, Shang-Lin; Li, Kuang-Yu; Huang, Po-Tsang; Hwang, Wei; Tu, Ming-Hsien; Lung, Sheng-Chi; Peng, Wei-Sheng; Huang, Huan-Shun; Lee, Kuen-Di; Kao, Yung-Shin; Chuang, Ching-Te; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2006A 1.7mW all digital phase-locked loop with new gain generator and low power DCOChao, Tzu-Chiang; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2007A 1.9mW portable ADPLL-based frequency synthesizer for high speed clock generationChang, Ming-Hung; Yang, Zong-Xi; Hwang, Wei; 電子與資訊研究中心; Microelectronics and Information Systems Research Center
2014A 16kB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOSKuo, Ming-Zhang; Hsieh, Henry; Dhong, Sang; Yang, Ping-Lin; Lin, Cheng-Chung; Tseng, Ryan; Huang, Kevin; Wang, Min-Jer; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
20062-l.evel FIFO architecture design for switch fabrics in network-on-chipHuang, Po-Tsang; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A 2.1-mu W 0.3V-1.0V Wide Locking Range Multiphase DLL Using Self-Estimated SAR AlgorithmChang, Yi-Ming; Chang, Ming-Hung; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-20142.5D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural-Sensing ApplicationsHuang, Po-Tsang; Chou, Lei-Chun; Huang, Teng-Chieh; Wu, Shang-Lin; Wang, Tang-Shuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chen, Kuan-Neng; Chiou, Jin-Chern; Chuang, Ching-Te; Hwang, Wei; Chen, Kuo-Hua; Chiu, Chi-Tsung; Cheng, Ming-Hsiang; Lin, Yueh-Lung; Tong, Ho-Ming; 交大名義發表; National Chiao Tung University
1-Dec-20142.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing ApplicationsHuang, Po-Tsang; Wu, Shang-Lin; Huang, Yu-Chieh; Chou, Lei-Chun; Huang, Teng-Chieh; Wang, Tang-Hsuan; Lin, Yu-Rou; Cheng, Chuan-An; Shen, Wen-Wei; Chuang, Ching-Te; Chen, Kuan-Neng; Chiou, Jin-Chern; Hwang, Wei; Tong, Ho-Ming; 交大名義發表; National Chiao Tung University
2007A 256x128 energy-efficient TCAM with novel low power schemesHuang, Po-Tsang; Chang, Shu-Wei; Liu, Wen-Yen; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
201528 奈米高介電係數金屬閘極製程操縱在 近/次臨界電壓之256kb 6T 靜態隨機存取記憶體李光宇; Li, Kuang-Yu; 莊景德; 黃威; Chuang,Ching-Te; Hwang, Wei; 電子工程學系 電子研究所
201628nm Ultra-Low Power Near-/Sub- threshold First-In-First-Out (FIFO) Memory for Multi-Bio-Signal Sensing PlatformsHsu, Wei-Shen; Huang, Po-Tsang; Wu, Shang-Lin; Chuang, Ching-Te; Hwang, Wei; Tu, Ming-Hsien; Yin, Ming-Yu; 電子工程學系及電子研究所; 電機工程學系; Department of Electronics Engineering and Institute of Electronics; Department of Electrical and Computer Engineering
201728奈米近臨界電壓使用12顆電晶體搭配短反或閘型匹配線之管線化的三態內容可定址記憶體陳俊丞; 莊景德; 黃威; Chen, Jyun-Cheng; Chuang, Ching-Te; Hwang, Wei; 電子研究所
2008A 300-mV 36-mu W Multiphase Dual Digital Clock Output Generator with Self-CalibrationChang, Ming-Hung; Chuang, Li-Pu; Chang, I-Ming; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Dec-2014A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-AssistLien, Nan-Chun; Chu, Li-Wei; Chen, Chien-Hen; Yang, Hao-I.; Tu, Ming-Hsien; Kan, Paul-Sen; Hu, Yong-Jyun; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2013A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting ControlLiao, Wei-Nan; Lien, Nan-Chun; Chang, Chi-Shin; Chu, Li-Wei; Yang, Hao-I; Chuang, Ching-Te; Jou, Shyh-Jye; Hwang, Wei; Tu, Ming-Hsien; Huang, Huan-Shun; Wang, Jian-Hao; Kan, Paul-Sen; Hu, Yong-Jyun; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2013A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-AssistChang, Chi-Shin; Yang, Hao-I; Liao, Wei-Nan; Lin, Yi-Wei; Lien, Nan-Chun; Chen, Chien-Hen; Chuang, Ching-Te; Hwang, Wei; Jou, Shyh-Jye; Tu, Ming-Hsien; Huang, Huan-Shun; Hu, Yong-Jyun; Kan, Paul-Sen; Cheng, Cheng-Yo; Wang, Wei-Chang; Wang, Jian-Hao; Lee, Kuen-Di; Chen, Chia-Cheng; Shih, Wei-Chiang; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loopChuang, Li-Pu; Chang, Ming-Hung; Huang, Po-Tsang; Kan, Chih-Hao; Hwang, Wei; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics