Browsing by Author Hsieh, E. R.

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Issue DateTitleAuthor(s)
2014A Comprehensive Transport Model for High Performance HEMTs Considering the Parasitic Resistance and Capacitance EffectsHung, C. M.; Li, K. C.; Hsieh, E. R.; Wang, C. T.; Kou, C. I.; Chang, Edward Y.; Chung, Steve S.; 材料科學與工程學系; 電子工程學系及電子研究所; Department of Materials Science and Engineering; Department of Electronics Engineering and Institute of Electronics
2015The Demonstration of Low-cost and Logic Process Fully-Compatible OTP Memory on Advanced HKMG CMOS with a Newly found Dielectric Fuse BreakdownHsieh, E. R.; Huang, Z. H.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; Yew, T. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2015Design of Complementary Tilt-gate TFETs with SiGe/Si and III-V Integrations Feasible for Ultra-low-power ApplicationsHsieh, E. R.; Lin, Y. S.; Zhao, Y. B.; Liu, C. H.; Chien, C. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E)Chung, Steve S.; Hsieh, E. R.; Liu, P. W.; Chiang, W. T.; Tsai, S. H.; Tsai, T. L.; Huang, R. M.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2018An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AIKuo, J. L.; Chen, H. W.; Hsieh, E. R.; Chung, Steve S.; Chen, T. P.; Huang, S. A.; Chen, T. J.; Cheng, Osbert; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2014The Experimental Demonstration of the BTI-Induced Breakdown Path in 28nm High-k Metal Gate Technology CMOS DevicesHsieh, E. R.; Lu, P. Y.; Chung, Steve S.; Chang, K. Y.; Liu, C. H.; Ke, J. C.; Yang, C. W.; Tsai, C. T.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016Experimental Techniques on the Understanding of the Charge Loss in a SONOS Nitride-storage Nonvolatile MemoryHsieh, E. R.; Wang, H. T.; Chung, Steve S.; Chang, Wayne; Wang, S. D.; Chen, C. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2013Gate Current Variation: A New Theory and Practice on Investigating the Off-State Leakage of Trigate MOSFETs and the Power Dissipation of SRAMHsieh, E. R.; Lin, S. T.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Jung, L. T.; 電機工程學系; Department of Electrical and Computer Engineering
1-Jan-2017Geometric Variation: A Novel Approach to Examine the Surface Roughness and the Line Roughness Effects in Trigate FinFETsHsieh, E. R.; Fan, Y. C.; Liu, C. H.; Chung, Steve S.; Huang, R. M.; Tsai, C. T.; Yew, T. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2017The Guideline on Designing Face-tunneling FET for Large-scale-device Applications in IoTHsieh, E. R.; Lee, J. W.; Lee, M. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring High Speed, Ultra-low power, and Low Voltage OperationHsieh, E. R.; Chuang, C. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2017The Issues on the Power Consumption of Trigate FinFET: The Design and Manufacturing GuidelinesChung, Steve S.; Hsieh, E. R.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
26-Nov-2012The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistorsHsieh, E. R.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable ReliabilityChung, Steve S.; Hsieh, E. R.; Huang, D. C.; Lai, C. S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic RegimeHsieh, E. R.; Chung, Steve S.; Liu, P. W.; Chiang, W. T.; Tsai, C. H.; Teng, W. Y.; Li, C. I.; Kuo, T. F.; Wang, Y. R.; Yang, C. L.; Tsai, C. T.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2008New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and BeyondHsieh, E. R.; Chung, Steve S.; Lin, Y. H.; Tsai, C. H.; Liu, P. W.; Tsai, C. T.; Ma, G. H.; Chien, S. C.; Sun, S. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2009A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise MeasurementLin, M. H.; Hsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Liu, P. W.; Lin, Y. H.; Tsai, C. T.; Ma, G. H.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2011New Observations on the Physical Mechanism of Vth-Variation in Nanoscale CMOS Devices After Long Term StressHsieh, E. R.; Chung, Steve S.; Tsai, C. H.; Huang, R. M.; Tsai, C. T.; Liang, C. W.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
2016A New Variation Plot to Examine the Interfacial-dipole Induced Work-function Variation in Advanced High-k Metal-gate CMOS DevicesHsieh, E. R.; Wang, Y. D.; Chung, Steve S.; Ke, J. C.; Yang, C. W.; Hsu, S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics
1-Jan-2017A Novel Design of P-N Staggered Face-tunneling TFET Targeting for Low Power and Appropriate Performance ApplicationsHsieh, E. R.; Fan, Y. C.; Chang, K. Y.; Liu, C. H.; Chien, C. H.; Chung, Steve S.; 電子工程學系及電子研究所; Department of Electronics Engineering and Institute of Electronics